1. Field of the Invention
The present invention relates to a frequency synthesizer which outputs a signal synchronized with a reference signal.
2. Description of the Related Art
There has been known a frequency synthesizer which uses a PLL (Phase Locked Loop) circuit to generate a signal synchronized with a reference signal. There is a digital frequency synthesizer which uses a DDS (Direct Digital Synthesizer). Such a synthesizer stores waveform data of trigonometric functions in a ROM (Read Only Memory), reads out the waveform data and performs D/A conversion on the waveform data, thereby generating a sine wave.
FIG. 11 illustrates the structure of a conventional frequency synthesizer which uses a DDS. As illustrated in FIG. 11, the conventional frequency synthesizer comprises an adder 26, a ROM 27, a D/A converter 28, an LPF (Low Pass Filter) 29, a comparator 9, and a PLL circuit 30. The adder 26, the ROM 27, the D/A converter 28, and the LPF 29 constitute a DDS circuit 200.
The conventional frequency synthesizer with the DDS illustrated in FIG. 11 first gives, as an input, the adder 26 a numerical value corresponding to a frequency to be generated. The adder 26 performs cumulative addition on the frequency data, and supplies the ROM 27 with a phase data string as an address. The ROM 27 acquires waveform data of a sine wave from the addresses sequentially designated by the phase data string, and supplies that waveform data to the D/A converter 28. The D/A converter 28 converts the received waveform data to an analog waveform, and supplies that analog waveform to the LPF 29. The analog output wave includes folded noise components and has a stepwise waveform. The LPF 29 supplies the comparator 9 a precise sinusoidal waveform obtained by eliminating the folded noise components. The comparator 9 compares the sinusoidal waveform supplied from the LPF 29 with a predetermined reference voltage, and supplies the PLL circuit 30 a pulse train indicating the polarity of the sinusoidal waveform with respect to the reference voltage. That is, the comparator 9 outputs the pulse train which specifies a phase at a transition point of the polarity of the sinusoidal waveform with respect to the reference voltage. The PLL circuit 30 outputs an output signal which is synchronized with the pulse train, and has a frequency equal to an integral-multiplied frequency of the pulse train. To improve the noise performance of the signal finally output from the PLL circuit 30 by that system, it is necessary to reduce the frequency multiplication by the PLL circuit 30 as small as possible. To that end, it is necessary to increase the frequency of the sine wave synthesized by the DDS circuit 200 as much as possible. The DDS circuit 200, however, requires the high-order and complex LPF 29 to eliminate folded spectrums if the frequency to be synthesized is not sufficiently low with respect to the operating frequency of the circuit. Even if an attempt is made to set the operating frequency of the circuit high, it is impossible to set that operating frequency higher than the operation limit of the D/A converter 28. Because of those reasons, there is a limitation to the frequency of the output signal of the DDS circuit 200.
There is another frequency synthesizer which uses waveform data of a triangular wave instead of sinusoidal waveform data, and performs linear interpolation to provide a signal synchronized with the reference signal without a ROM (see, for example, P3-4, and FIG. 1 of Unexamined Japanese Patent Application KOKAI Publication No. 05-206732).
The linear-interpolation type frequency synthesizer requires no ROM, and generates no folded spectrum. Accordingly, the frequency synthesizer does not require a filter for eliminating a folded spectrum.
The conventional linear-interpolation type frequency synthesizer, however, requires adjustment of the gain of the integrator which constitutes the linear interpolation circuit in accordance with the operating frequency of the circuit. If there is an error in that adjustment, the linear interpolation is not carried out precisely, resulting in generation of jitters in the output pulse train.
An offset error may be observed on the D/A converter included in the reference signal generator. Because of the offset error, the zero cross timing of the output voltage is shifted from the zero cross timing in a case where there is no offset error (ideal value). The shift of the zero cross timing becomes larger as time elapses from the reset timing. In general, the linear interpolation circuit is reset in synchronization with the system clock. Because the relative positions of the system clock and the zero cross timing always change, the time interval between the reset timing and the zero cross timing always changes, too.
Accordingly, there is a change in time lag between the zero cross timing obtained in a case where the D/A converter has the offset error, and the normal zero cross timing (without an offset error). This results in generation of jitters in the output pulse train.
FIG. 12A illustrates a VCO (Voltage Controlled Oscillator) control voltage of the PLL circuit which is controlled based on the reference timing signal, shown in FIG. 12B, that is the output pulse train with the jitters originated from the offset error of the D/A converter. As illustrated in FIGS. 12A and 12B, the VCO control voltage changes in accordance with the reference timing signal.
In response to that change, the frequency of the output signal changes. FIG. 13 illustrates the result of simulation of the frequency change characteristic when that frequency changes. The conditions of the simulation are the phase comparison frequency of 8051 kHz, the frequency division of the frequency of the PLL circuit by a division factor of 50, the 0.3% offset error of the D/A converter, and the secondary distortion of 0.3%. The range of the frequency change is 213 kHz at a period of 2.9 μs. The characteristic of the frequency spectrums becomes like one as illustrated in FIG. 14, and the frequency characteristic includes jamming (noise; spurious noise) spectrums, thereby deteriorating the frequency characteristic (noise performance).
In the conventional frequency synthesizer with the DDS, if the D/A converter has a non-linear offset error, noise spectrums due to the high-frequency distortion are generated. The noise spectrums, however, can be eliminated by narrowing the bandwidth of an analog filter (the LPF 29 in FIG. 11) which eliminates folded noise components.
The frequency synthesizer using triangular waveform data cannot use such an analog filter. Accordingly, the nonlinear characteristic of an analog signal due to the offset error of the D/A converter cannot be adjusted. Therefore, the frequency synthesizer requires a high precision D/A converter.